Increased circuit density is an ongoing goal of manufacturers of semiconductor devices. One long-favored configuration is an assembly of vertically stacked semiconductor dice, at least some of which are interconnected electrically and the stacked die assembly being mechanically and electrically connected to higher level packaging, such as an interposer or other substrate bearing conductive traces.
One configuration employing a plurality of stacked semiconductor dice is a Micropillar Grid Array Package (“MPGA”). Such a package comprises a stack of a plurality (for example four (4)) of dynamic random access (DRAM) semiconductor memory dice vertically interconnected from an uppermost die to a lowermost die, and a plurality of electrically conductive pillars extending from the underside of the lowermost memory die for connection to a logic die or a System on a Chip (SoC) die.
The provider of the logic die or the SoC die conventionally mounts their device to an interposer, such as a ball grid array (BGA) substrate, the logic or SoC die including conductive through vias for connection to the conductive pillars on the underside of the MPGA. The MPGA is mounted to the logic die or SoC die on the interposer and the assembly is then overmolded with an encapsulant into a finished Ball Grid Array (BGA) package.
The aforementioned configuration, implemented as a so-called “Wide I/O” memory device, enables fast memory access, and reduces power requirements.
One particularly promising configuration of an MPGA is a die assembly which incorporates a high-speed logic die below a vertical stack of DRAM dice interconnected with through-silicon vias (TSVs). The DRAM dice are configured specifically to only handle data, while the logic die provides all DRAM control within the die assembly. The design is expected to reduce latency, and greatly improve bandwidth and speed, while offering significantly reduced power demand and physical space requirements and providing flexibility for multiple platforms and application through use of different logic dice. One such implementation of a die assembly as described above may be characterized as a Memory Cube DRAM (MCDRAM) comprising a thermally conductive overmold over the DRAM dice and in contact with the logic die where it extends peripherally beyond the stack of DRAM dice. Another implementation of such a die assembly may be characterized as a Hybrid Memory Cube (HMC), wherein a lid is disposed over the stack of DRAM dice in peripheral contact with the logic die.
End products of the above designs will find a wide variety of applications including, among others, in mobile electronic devices such as so-called “smart phones,” laptop and notebook computers, supercomputers, BLACKBERRY® devices, iPHONE® and iPAD® devices, and DROID® devices.
One significant concern with regard to implementation of the above-referenced designs is providing good adhesion, sufficient to withstand reliability stress testing, between bond pads of a semiconductor die and small diameter pillars at tight pitches employed to provide reliable electrical connections to another semiconductor die, interposer or other substrate above or below the semiconductor die in a stack.
Referring to FIG. 1, in a conventional pillar on pad interconnect structure 100 for a semiconductor die 102 comprises an electrically conductive element 104 in the form of a pillar including a copper material 106 of about 30 μm diameter, a nickel material 108 thereover, and a solder material 110, such as a SnAg solder, over nickel material 108. Bond pad 112 on active surface 114 of semiconductor die 102 is surrounded by passivation material 116, for example of at least one of SiNx and SiOx. A polymer repassivation material 118 is located over passivation material 116, extending over bond pad 112 and leaving about a 9 μm diameter opening for contact of bond pad 112 with 30 μm diameter copper material 106. During the aforementioned stress testing, and as depicted in FIG. 2, due to the relatively small exposed surface area of bond pad 112 afforded by polymer repassivation material 118, copper material 106 of conductive element 104 lifts off bond pad 112, creating an open circuit OC between bond pad 112, which is in electrical contact with circuitry of semiconductor die 102, for example conductive via 120. The limited structural support provided to conductive element 104 peripheral to the area of contact with bond pad 112 by the relatively soft and plastic nature of the polymer repassivation material 118 exacerbates the connectivity problem during thermocompression bonding employed to reflow solder material 110 to attach and electrically connect semiconductor die 102 to another component.
In a recent attempt by the inventors to remedy the above-referenced problem, which attempt is not admitted to be prior art or to otherwise comprise a public disclosure, 30 μm conductive elements were formed directly on bond pads in the absence of polymer repassivation material. However, when solder material was reflowed, the solder material wet along sides of the pillars past the nickel material and copper material to contact the bond pads, causing failure of the semiconductor dice due to formation of intermetallic compounds with the bond pad material, swelling of these compounds, and electrical shorting with circuitry under bond pads. In addition, in some instances the wetting of solder material down the pillars resulted in inadequate solder mass to connect to a landing pad on an adjacent component during reflow.